ICS TriplexT8110B Core Function
Triple Modular Redundancy (TMR) and Fault Tolerance
Employs Triple Modular Redundancy (TMR) and Hardware Implemented Fault Tolerance (HIFT) architectures to ensure continuous operation even during hardware failures. This design uses three synchronized processors for majority voting (3-2-0 voting), allowing the system to mask faults and maintain functionality.
Supports hot-swappable replacement, enabling module replacement without system shutdown or reprogramming.
High-Performance Processing and Memory
Processor Clock: 100 MHz for efficient execution of control algorithms.
Memory Configuration:
DRAM: 16 MB EDO (Extended Data Out) for fast data access.
EPROM: 512 kB for firmware storage.
Flash: 2 MB for program updates.
NVRAM: 128 kB to retain critical variables during power loss.
Retained Variable Storage: Supports retention of Boolean (1 byte), analog (4 bytes), and timer (5 bytes) variables.
Robust Communication Interfaces
Triple-Redundant Inter-Module Bus: Ensures reliable data exchange with I/O modules and other system components.
Serial Ports:
Front-panel RS232 for diagnostics and programming.
Two RS422/485 ports (configurable as 2- or 4-wire) and one RS485 2-wire connection (exclusive to T8110B).
Time Synchronization: Supports IRIG-B002/B122 signals for precise synchronization in distributed systems.
